Files
ESP-Miner/components/asic/include/pll.h
mutatrum e5c317fb97 Improve PLL calculation for BM1366/BM1368/BM1370 (#1051)
* Accept and store float frequency values

* Unify PLL resolver for 1366/1368/1370

Pick the closest frequency to the requested target. If there are multiple PLL settings, pick the one with first the lowest VDO frequency, and finally the lowest posdividers.

Merged frequency ramp start and loop. This solves overshooting when requesting a target frequency within the current step size. It also eliminates the duplicate setting of the target frequency is that's on a step boundary.

Cleaned up several unused defines.

* Restore postdiv2 < postdiv1 condition for BM1368 and BM1370

* Whitespace

* Clean up intermediate functions

Simplify frequency_transition further, finally fix overshoot

* Code cleanup

* Add debug logging for BM1397

* Fix log

* Flip postdiv condition for readability

* Add test

* Fix BM1370 fb_range

* EOF line in test_pll.c
2025-08-07 13:16:36 +02:00

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C

#ifndef PLL_H_
#define PLL_H_
#include <stdint.h>
#include <stdbool.h>
#define FREQ_MULT 25.0 // MHz
void pll_get_parameters(float target_freq, uint16_t fb_divider_min, uint16_t fb_divider_max,
uint8_t *fb_divider, uint8_t *refdiv, uint8_t *postdiv1, uint8_t *postdiv2,
float *actual_freq);
#endif /* PLL_H_ */