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https://github.com/Next-Flip/Momentum-Firmware.git
synced 2025-10-04 11:07:02 +02:00
319 lines
12 KiB
C
319 lines
12 KiB
C
#include "iso14443_4_layer.h"
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#include <furi.h>
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// EMV Specific masks
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#define ISO14443_4_BLOCK_PCB_I_ (0U << 6)
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#define ISO14443_4_BLOCK_PCB_R_ (2U << 6)
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#define ISO14443_4_BLOCK_PCB_TYPE_MASK (3U << 6)
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#define ISO14443_4_BLOCK_PCB_S_WTX (3U << 4)
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#define ISO14443_4_BLOCK_PCB_S (3U << 6)
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//
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#define ISO14443_4_BLOCK_PCB (1U << 1)
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#define ISO14443_4_BLOCK_PCB_MASK (0x03)
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#define ISO14443_4_BLOCK_PCB_I (0U)
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#define ISO14443_4_BLOCK_PCB_I_MASK (1U << 1)
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#define ISO14443_4_BLOCK_PCB_I_ZERO_MASK (7U << 5)
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#define ISO14443_4_BLOCK_PCB_I_NAD_OFFSET (2)
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#define ISO14443_4_BLOCK_PCB_I_CID_OFFSET (3)
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#define ISO14443_4_BLOCK_PCB_I_CHAIN_OFFSET (4)
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#define ISO14443_4_BLOCK_PCB_I_NAD_MASK (1U << ISO14443_4_BLOCK_PCB_I_NAD_OFFSET)
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#define ISO14443_4_BLOCK_PCB_I_CID_MASK (1U << ISO14443_4_BLOCK_PCB_I_CID_OFFSET)
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#define ISO14443_4_BLOCK_PCB_I_CHAIN_MASK (1U << ISO14443_4_BLOCK_PCB_I_CHAIN_OFFSET)
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#define ISO14443_4_BLOCK_PCB_R_MASK (5U << 5)
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#define ISO14443_4_BLOCK_PCB_R_NACK_OFFSET (4)
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#define ISO14443_4_BLOCK_PCB_R_CID_OFFSET (3)
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#define ISO14443_4_BLOCK_PCB_R_CID_MASK (1U << ISO14443_4_BLOCK_PCB_R_CID_OFFSET)
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#define ISO14443_4_BLOCK_PCB_R_NACK_MASK (1U << ISO14443_4_BLOCK_PCB_R_NACK_OFFSET)
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#define ISO14443_4_BLOCK_PCB_S_MASK (3U << 6)
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#define ISO14443_4_BLOCK_PCB_S_CID_OFFSET (3)
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#define ISO14443_4_BLOCK_PCB_S_WTX_DESELECT_OFFSET (4)
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#define ISO14443_4_BLOCK_PCB_S_CID_MASK (1U << ISO14443_4_BLOCK_PCB_R_CID_OFFSET)
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#define ISO14443_4_BLOCK_PCB_S_WTX_DESELECT_MASK (3U << ISO14443_4_BLOCK_PCB_S_WTX_DESELECT_OFFSET)
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#define ISO14443_4_BLOCK_CID_MASK (0x0F)
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#define ISO14443_4_BLOCK_PCB_BITS_ACTIVE(pcb, mask) (((pcb) & (mask)) == (mask))
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#define ISO14443_4_BLOCK_PCB_IS_I_BLOCK(pcb) \
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(ISO14443_4_BLOCK_PCB_BITS_ACTIVE(pcb, ISO14443_4_BLOCK_PCB_I_MASK) && \
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(((pcb) & ISO14443_4_BLOCK_PCB_I_ZERO_MASK) == 0))
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#define ISO14443_4_BLOCK_PCB_IS_R_BLOCK(pcb) \
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ISO14443_4_BLOCK_PCB_BITS_ACTIVE(pcb, ISO14443_4_BLOCK_PCB_R_MASK)
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#define ISO14443_4_BLOCK_PCB_IS_S_BLOCK(pcb) \
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ISO14443_4_BLOCK_PCB_BITS_ACTIVE(pcb, ISO14443_4_BLOCK_PCB_S_MASK)
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#define ISO14443_4_BLOCK_PCB_IS_CHAIN_ACTIVE(pcb) \
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ISO14443_4_BLOCK_PCB_BITS_ACTIVE(pcb, ISO14443_4_BLOCK_PCB_I_CHAIN_MASK)
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#define ISO14443_4_BLOCK_PCB_R_NACK_ACTIVE(pcb) \
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ISO14443_4_BLOCK_PCB_BITS_ACTIVE(pcb, ISO14443_4_BLOCK_PCB_R_NACK_MASK)
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#define ISO14443_4_LAYER_NAD_NOT_SUPPORTED ((uint8_t) - 1)
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#define ISO14443_4_LAYER_NAD_NOT_SET ((uint8_t) - 2)
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struct Iso14443_4Layer {
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uint8_t pcb;
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uint8_t pcb_prev;
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// Listener specific
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uint8_t cid;
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uint8_t nad;
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};
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static inline void iso14443_4_layer_update_pcb(Iso14443_4Layer* instance, bool toggle_num) {
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instance->pcb_prev = instance->pcb;
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if(toggle_num) {
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instance->pcb ^= (uint8_t)0x01;
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}
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}
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Iso14443_4Layer* iso14443_4_layer_alloc(void) {
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Iso14443_4Layer* instance = malloc(sizeof(Iso14443_4Layer));
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iso14443_4_layer_reset(instance);
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return instance;
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}
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void iso14443_4_layer_free(Iso14443_4Layer* instance) {
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furi_assert(instance);
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free(instance);
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}
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void iso14443_4_layer_reset(Iso14443_4Layer* instance) {
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furi_assert(instance);
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instance->pcb_prev = 0;
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instance->pcb = ISO14443_4_BLOCK_PCB_I | ISO14443_4_BLOCK_PCB;
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instance->cid = ISO14443_4_LAYER_CID_NOT_SUPPORTED;
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instance->nad = ISO14443_4_LAYER_NAD_NOT_SUPPORTED;
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}
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void iso14443_4_layer_set_i_block(Iso14443_4Layer* instance, bool chaining, bool CID_present) {
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uint8_t block_pcb = instance->pcb & ISO14443_4_BLOCK_PCB_MASK;
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instance->pcb = ISO14443_4_BLOCK_PCB_I | (chaining << ISO14443_4_BLOCK_PCB_I_CHAIN_OFFSET) |
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(CID_present << ISO14443_4_BLOCK_PCB_I_CID_OFFSET) | block_pcb;
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}
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void iso14443_4_layer_set_r_block(Iso14443_4Layer* instance, bool acknowledged, bool CID_present) {
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furi_assert(instance);
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uint8_t block_pcb = instance->pcb & ISO14443_4_BLOCK_PCB_MASK;
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instance->pcb = ISO14443_4_BLOCK_PCB_R_MASK |
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(!acknowledged << ISO14443_4_BLOCK_PCB_R_NACK_OFFSET) |
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(CID_present << ISO14443_4_BLOCK_PCB_R_CID_OFFSET) | block_pcb;
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}
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void iso14443_4_layer_set_s_block(Iso14443_4Layer* instance, bool deselect, bool CID_present) {
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furi_assert(instance);
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uint8_t des_wtx = !deselect ? (ISO14443_4_BLOCK_PCB_S_WTX_DESELECT_MASK) : 0;
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instance->pcb = ISO14443_4_BLOCK_PCB_S_MASK | des_wtx |
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(CID_present << ISO14443_4_BLOCK_PCB_S_CID_OFFSET) | ISO14443_4_BLOCK_PCB;
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}
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void iso14443_4_layer_encode_command(
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Iso14443_4Layer* instance,
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const BitBuffer* input_data,
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BitBuffer* block_data) {
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furi_assert(instance);
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bit_buffer_append_byte(block_data, instance->pcb);
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bit_buffer_append(block_data, input_data);
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iso14443_4_layer_update_pcb(instance, true);
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}
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static inline uint8_t iso14443_4_layer_get_response_pcb(const BitBuffer* block_data) {
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const uint8_t* data = bit_buffer_get_data(block_data);
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return data[0];
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}
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bool iso14443_4_layer_decode_response(
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Iso14443_4Layer* instance,
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BitBuffer* output_data,
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const BitBuffer* block_data) {
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furi_assert(instance);
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bool ret = false;
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do {
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if(ISO14443_4_BLOCK_PCB_IS_R_BLOCK(instance->pcb_prev)) {
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const uint8_t response_pcb = iso14443_4_layer_get_response_pcb(block_data);
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ret = (ISO14443_4_BLOCK_PCB_IS_R_BLOCK(response_pcb)) &&
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(!ISO14443_4_BLOCK_PCB_R_NACK_ACTIVE(response_pcb));
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instance->pcb &= ISO14443_4_BLOCK_PCB_MASK;
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iso14443_4_layer_update_pcb(instance, true);
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} else if(ISO14443_4_BLOCK_PCB_IS_CHAIN_ACTIVE(instance->pcb_prev)) {
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const uint8_t response_pcb = iso14443_4_layer_get_response_pcb(block_data);
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ret = (ISO14443_4_BLOCK_PCB_IS_R_BLOCK(response_pcb)) &&
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(!ISO14443_4_BLOCK_PCB_R_NACK_ACTIVE(response_pcb));
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instance->pcb &= ~(ISO14443_4_BLOCK_PCB_I_CHAIN_MASK);
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} else if(ISO14443_4_BLOCK_PCB_IS_S_BLOCK(instance->pcb_prev)) {
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ret = bit_buffer_starts_with_byte(block_data, instance->pcb_prev);
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if(bit_buffer_get_size_bytes(block_data) > 1)
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bit_buffer_copy_right(output_data, block_data, 1);
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} else {
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if(!bit_buffer_starts_with_byte(block_data, instance->pcb_prev)) break;
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bit_buffer_copy_right(output_data, block_data, 1);
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ret = true;
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}
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} while(false);
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return ret;
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}
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Iso14443_4aError iso14443_4_layer_decode_response_pwt_ext(
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Iso14443_4Layer* instance,
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BitBuffer* output_data,
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const BitBuffer* block_data) {
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furi_assert(instance);
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Iso14443_4aError ret = Iso14443_4aErrorProtocol;
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bit_buffer_reset(output_data);
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do {
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const uint8_t pcb_field = bit_buffer_get_byte(block_data, 0);
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const uint8_t block_type = pcb_field & ISO14443_4_BLOCK_PCB_TYPE_MASK;
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switch(block_type) {
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case ISO14443_4_BLOCK_PCB_I_:
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if(pcb_field == instance->pcb_prev) {
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bit_buffer_copy_right(output_data, block_data, 1);
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ret = Iso14443_4aErrorNone;
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} else {
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// send original request again
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ret = Iso14443_4aErrorSendExtra;
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}
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break;
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case ISO14443_4_BLOCK_PCB_R_:
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// TODO
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break;
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case ISO14443_4_BLOCK_PCB_S:
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if((pcb_field & ISO14443_4_BLOCK_PCB_S_WTX) == ISO14443_4_BLOCK_PCB_S_WTX) {
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const uint8_t inf_field = bit_buffer_get_byte(block_data, 1);
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//const uint8_t power_level = inf_field >> 6;
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const uint8_t wtxm = inf_field & 0b111111;
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//uint32_t fwt_temp = MIN((fwt * wtxm), fwt_max);
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bit_buffer_append_byte(
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output_data,
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ISO14443_4_BLOCK_PCB_S | ISO14443_4_BLOCK_PCB_S_WTX | ISO14443_4_BLOCK_PCB);
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bit_buffer_append_byte(output_data, wtxm);
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ret = Iso14443_4aErrorSendExtra;
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}
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break;
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}
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} while(false);
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if(ret != Iso14443_4aErrorNone) {
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FURI_LOG_RAW_T("RAW RX:");
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for(size_t x = 0; x < bit_buffer_get_size_bytes(block_data); x++) {
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FURI_LOG_RAW_T("%02X ", bit_buffer_get_byte(block_data, x));
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}
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FURI_LOG_RAW_T("\r\n");
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}
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return ret;
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}
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void iso14443_4_layer_set_cid(Iso14443_4Layer* instance, uint8_t cid) {
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instance->cid = cid;
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}
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void iso14443_4_layer_set_nad_supported(Iso14443_4Layer* instance, bool nad) {
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instance->nad = nad ? 0 : ISO14443_4_LAYER_NAD_NOT_SUPPORTED;
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}
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Iso14443_4LayerResult iso14443_4_layer_decode_command(
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Iso14443_4Layer* instance,
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const BitBuffer* input_data,
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BitBuffer* block_data) {
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furi_assert(instance);
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uint8_t prologue_len = 0;
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instance->pcb = bit_buffer_get_byte(input_data, prologue_len++);
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if(ISO14443_4_BLOCK_PCB_IS_I_BLOCK(instance->pcb)) {
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if(instance->pcb & ISO14443_4_BLOCK_PCB_I_CID_MASK) {
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const uint8_t cid = bit_buffer_get_byte(input_data, prologue_len++) &
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ISO14443_4_BLOCK_CID_MASK;
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if(instance->cid == ISO14443_4_LAYER_CID_NOT_SUPPORTED || cid != instance->cid) {
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return Iso14443_4LayerResultSkip;
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}
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} else if(instance->cid != ISO14443_4_LAYER_CID_NOT_SUPPORTED && instance->cid != 0) {
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return Iso14443_4LayerResultSkip;
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}
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// TODO: properly handle block chaining
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if(instance->pcb & ISO14443_4_BLOCK_PCB_I_NAD_MASK) {
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if(instance->nad == ISO14443_4_LAYER_NAD_NOT_SUPPORTED) {
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return Iso14443_4LayerResultSkip;
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}
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instance->nad = bit_buffer_get_byte(input_data, prologue_len++);
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}
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bit_buffer_copy_right(block_data, input_data, prologue_len);
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iso14443_4_layer_update_pcb(instance, false);
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return Iso14443_4LayerResultData;
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} else if(ISO14443_4_BLOCK_PCB_IS_S_BLOCK(instance->pcb)) {
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if(instance->pcb & ISO14443_4_BLOCK_PCB_S_CID_MASK) {
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const uint8_t cid = bit_buffer_get_byte(input_data, prologue_len++) &
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ISO14443_4_BLOCK_CID_MASK;
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if(instance->cid == ISO14443_4_LAYER_CID_NOT_SUPPORTED || cid != instance->cid) {
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return Iso14443_4LayerResultSkip;
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}
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} else if(instance->cid != ISO14443_4_LAYER_CID_NOT_SUPPORTED && instance->cid != 0) {
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return Iso14443_4LayerResultSkip;
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}
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if((instance->pcb & ISO14443_4_BLOCK_PCB_S_WTX_DESELECT_MASK) == 0) {
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// DESELECT
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bit_buffer_copy(block_data, input_data);
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return Iso14443_4LayerResultSend | Iso14443_4LayerResultHalt;
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} else {
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// WTX ACK or wrong value
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return Iso14443_4LayerResultSkip;
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}
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} else if(ISO14443_4_BLOCK_PCB_IS_R_BLOCK(instance->pcb)) {
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// TODO: properly handle R blocks while chaining
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iso14443_4_layer_update_pcb(instance, true);
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instance->pcb |= ISO14443_4_BLOCK_PCB_R_NACK_MASK;
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bit_buffer_reset(block_data);
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bit_buffer_append_byte(block_data, instance->pcb);
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iso14443_4_layer_update_pcb(instance, false);
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return Iso14443_4LayerResultSend;
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}
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return Iso14443_4LayerResultSkip;
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}
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bool iso14443_4_layer_encode_response(
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Iso14443_4Layer* instance,
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const BitBuffer* input_data,
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BitBuffer* block_data) {
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furi_assert(instance);
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if(ISO14443_4_BLOCK_PCB_IS_I_BLOCK(instance->pcb_prev)) {
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bit_buffer_append_byte(block_data, 0x00);
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if(instance->pcb_prev & ISO14443_4_BLOCK_PCB_I_CID_MASK) {
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bit_buffer_append_byte(block_data, instance->cid);
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}
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// TODO: properly handle block chaining and related R block responses
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if(instance->pcb_prev & ISO14443_4_BLOCK_PCB_I_NAD_MASK &&
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instance->nad != ISO14443_4_LAYER_NAD_NOT_SET) {
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bit_buffer_append_byte(block_data, instance->nad);
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instance->nad = ISO14443_4_LAYER_NAD_NOT_SET;
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} else {
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instance->pcb &= ~ISO14443_4_BLOCK_PCB_I_NAD_MASK;
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}
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instance->pcb &= ~ISO14443_4_BLOCK_PCB_I_CHAIN_MASK;
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bit_buffer_set_byte(block_data, 0, instance->pcb);
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bit_buffer_append(block_data, input_data);
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iso14443_4_layer_update_pcb(instance, false);
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return true;
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}
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return false;
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}
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