lavc/flacdsp: optimise RVV vector type for lpc32
This is pretty much the same as for lpc16, though it only improves half as large prediction orders. With 128-bit vectors, this gives: C V old V new 1 69.2 181.5 95.5 2 107.7 180.7 95.2 3 145.5 180.0 103.5 4 183.0 179.2 102.7 5 220.7 178.5 128.0 6 257.7 194.0 127.5 7 294.5 193.7 126.7 8 331.0 193.0 126.5 Larger prediction orders see no significant changes at that size.
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@ -71,17 +71,18 @@ av_cold void ff_flacdsp_init_riscv(FLACDSPContext *c, enum AVSampleFormat fmt,
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if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
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int vlenb = ff_get_rv_vlenb();
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if ((flags & AV_CPU_FLAG_RVB_BASIC) && vlenb >= 16)
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if ((flags & AV_CPU_FLAG_RVB_BASIC) && vlenb >= 16) {
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c->lpc16 = ff_flac_lpc16_rvv;
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# if (__riscv_xlen >= 64)
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if (flags & AV_CPU_FLAG_RVV_I64) {
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if (vlenb > 16)
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c->lpc32 = ff_flac_lpc32_rvv_simple;
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else
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c->lpc32 = ff_flac_lpc32_rvv;
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}
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if (flags & AV_CPU_FLAG_RVV_I64) {
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if (vlenb > 16)
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c->lpc32 = ff_flac_lpc32_rvv_simple;
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else
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c->lpc32 = ff_flac_lpc32_rvv;
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}
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# endif
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}
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c->wasted32 = ff_flac_wasted32_rvv;
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@ -76,22 +76,24 @@ func ff_flac_lpc32_rvv, zve64x
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ret
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endfunc
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func ff_flac_lpc32_rvv_simple, zve64x
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vsetivli zero, 1, e64, m1, ta, ma
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func ff_flac_lpc32_rvv_simple, zve64x, zbb
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vtype_vli t3, a2, t1, e64, ta, ma
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vntypei t2, t3
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vsetvl zero, a2, t3 // e64
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vmv.s.x v0, zero
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vsetvli zero, a2, e32, m4, ta, ma
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vsetvl zero, zero, t2 // e32
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vle32.v v8, (a1)
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sub a4, a4, a2
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vle32.v v16, (a0)
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sh2add a0, a2, a0
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1:
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vwmul.vv v24, v8, v16
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vsetvli zero, zero, e64, m8, ta, ma
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vsetvl zero, zero, t3 // e64
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vredsum.vs v24, v24, v0
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lw t0, (a0)
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addi a4, a4, -1
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vmv.x.s t1, v24
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vsetvli zero, zero, e32, m4, ta, ma
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vsetvl zero, zero, t2 // e32
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sra t1, t1, a3
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add t0, t0, t1
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vslide1down.vx v16, v16, t0
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