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ARM: NEON optimised vector_fmul

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Originally committed as revision 16867 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
Måns Rullgård
2009-01-30 23:13:15 +00:00
parent 8915009813
commit dd927e2e62
2 changed files with 44 additions and 0 deletions
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4
libavcodec/arm/dsputil_neon.c
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@@ -146,6 +146,8 @@ void ff_h264_idct_add8_neon(uint8_t **dest, const int *block_offset,
DCTELEM *block, int stride, DCTELEM *block, int stride,
const uint8_t nnzc[6*8]); const uint8_t nnzc[6*8]);
void ff_vector_fmul_neon(float *dst, const float *src, int len);
void ff_float_to_int16_neon(int16_t *, const float *, long); void ff_float_to_int16_neon(int16_t *, const float *, long);
void ff_float_to_int16_interleave_neon(int16_t *, const float **, long, int); void ff_float_to_int16_interleave_neon(int16_t *, const float **, long, int);
@@ -242,6 +244,8 @@ void ff_dsputil_init_neon(DSPContext *c, AVCodecContext *avctx)
c->h264_idct_add16intra = ff_h264_idct_add16intra_neon; c->h264_idct_add16intra = ff_h264_idct_add16intra_neon;
c->h264_idct_add8 = ff_h264_idct_add8_neon; c->h264_idct_add8 = ff_h264_idct_add8_neon;
c->vector_fmul = ff_vector_fmul_neon;
if (!(avctx->flags & CODEC_FLAG_BITEXACT)) { if (!(avctx->flags & CODEC_FLAG_BITEXACT)) {
c->float_to_int16 = ff_float_to_int16_neon; c->float_to_int16 = ff_float_to_int16_neon;
c->float_to_int16_interleave = ff_float_to_int16_interleave_neon; c->float_to_int16_interleave = ff_float_to_int16_interleave_neon;

40
libavcodec/arm/dsputil_neon_s.S
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@@ -609,3 +609,43 @@ function ff_float_to_int16_interleave_neon, export=1
vcvt.s32.f32 q1, q1, #16 vcvt.s32.f32 q1, q1, #16
b 6b b 6b
.endfunc .endfunc
function ff_vector_fmul_neon, export=1
mov r3, r0
subs r2, r2, #8
vld1.64 {d0-d3}, [r0,:128]!
vld1.64 {d4-d7}, [r1,:128]!
vmul.f32 q8, q0, q2
vmul.f32 q9, q1, q3
beq 3f
bics ip, r2, #15
beq 2f
1: subs ip, ip, #16
vld1.64 {d0-d1}, [r0,:128]!
vld1.64 {d4-d5}, [r1,:128]!
vmul.f32 q10, q0, q2
vld1.64 {d2-d3}, [r0,:128]!
vld1.64 {d6-d7}, [r1,:128]!
vmul.f32 q11, q1, q3
vst1.64 {d16-d19},[r3,:128]!
vld1.64 {d0-d1}, [r0,:128]!
vld1.64 {d4-d5}, [r1,:128]!
vmul.f32 q8, q0, q2
vld1.64 {d2-d3}, [r0,:128]!
vld1.64 {d6-d7}, [r1,:128]!
vmul.f32 q9, q1, q3
vst1.64 {d20-d23},[r3,:128]!
bne 1b
ands r2, r2, #15
beq 3f
2: vld1.64 {d0-d1}, [r0,:128]!
vld1.64 {d4-d5}, [r1,:128]!
vst1.64 {d16-d17},[r3,:128]!
vmul.f32 q8, q0, q2
vld1.64 {d2-d3}, [r0,:128]!
vld1.64 {d6-d7}, [r1,:128]!
vst1.64 {d18-d19},[r3,:128]!
vmul.f32 q9, q1, q3
3: vst1.64 {d16-d19},[r3,:128]!
bx lr
.endfunc