highperfocused/ffmpeg
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

lavc/flacdsp: do not assume maximum R-V VL

Browse Source 
This loop correctly assumes that VLMAX=16 (4x128-bit vectors
with 32-bit elements) and 32 >= pred_order > 16. We need to alternate
between VL=16 and VL=t2=pred_order-16 elements to add up to pred_order.

The current code requests AVL=a2=pred_order elements. In QEMU and on
thte K230 hardware, this sets VL=16 as we need. But the specification
merely guarantees that we get: ceil(AVL / 2) <= VL <= VLMAX. For
instance, if pred_order equals 27, we could end up with VL=14 or VL=15
instead of VL=16. So instead, request literally VLMAX=16.

(cherry picked from commit f8837465875205207bd281ecad9e4b9a12638c7e)
Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
This commit is contained in:
Rémi Denis-Courmont 2024-05-24 20:17:10 +03:00
parent 45765b7c2e
commit 2d514f5d48
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
libavcodec/riscv/flacdsp_rvv.S
View File

@ -55,11 +55,11 @@ func ff_flac_lpc32_rvv, zve32x
vle32.v v16, (a0)
sh2add a0, a2, a0
1:
vsetvli zero, a2, e32, m4, ta, ma
vsetvli t1, zero, e32, m4, ta, ma
vwmul.vv v24, v8, v16
vsetvli zero, t2, e32, m4, tu, ma
vwmacc.vv v24, v12, v20
vsetvli zero, a2, e64, m8, ta, ma
vsetvli t1, zero, e64, m8, ta, ma
vredsum.vs v24, v24, v0
lw t0, (a0)
addi a4, a4, -1